--- 2.3.28.orig/CREDITS Fri Nov 12 12:36:13 1999 +++ 2.3.28.work/CREDITS Fri Nov 19 17:23:11 1999 @@ -155,6 +155,14 @@ S: Notre Dame, Indiana S: USA +N: Greg Banks +E: gnb@linuxfan.com +D: IDT77105 ATM network driver +S: NEC Australia +S: 649-655 Springvale Rd +S: Mulgrave, Victoria 3170 +S: Australia + N: James Banks E: james.banks@caldera.com D: TLAN network driver @@ -1701,6 +1709,10 @@ N: Frederic Potter E: Frederic.Potter@masi.ibp.fr D: Some PCI kernel support + +N: Rui Prior +E: rprior@inescn.pt +D: ATM device driver for NICStAR based cards N: Stefan Probst E: sp@caldera.de --- 2.3.28.orig/Documentation/Configure.help Fri Nov 12 18:12:11 1999 +++ 2.3.28.work/Documentation/Configure.help Fri Nov 19 17:46:54 1999 @@ -3931,11 +3931,29 @@ overhead for timer synchronization and also per-packet overhead for time conversion. -IDT 77201 (NICStAR) +IDT 77201/11 (NICStAR) (ForeRunnerLE) CONFIG_ATM_NICSTAR The NICStAR chipset family is used in a large number of ATM NICs for 25 and for 155 Mbps, including IDT cards and the Fore ForeRunnerLE series. + +ForeRunner LE155 PHYsical layer +CONFIG_ATM_NICSTAR_USE_SUNI + Support for the S-UNI and compatible PHYsical layer chips. These are + found in most 155Mbps NICStAR based ATM cards, namely in the + ForeRunner LE155 cards. This driver provides detection of cable + removal and reinsertion and provides some statistics. This driver + doesn't have removal capability when compiled as a module, so if you + need that capability don't include S-UNI support (it's not needed to + make the card work). + +ForeRunner LE25 PHYsical layer +CONFIG_ATM_NICSTAR_USE_IDT77105 + Support for the PHYsical layer chip in ForeRunner LE25 cards. In + addition to cable removal/reinsertion detection, this driver allows + you to control the loopback mode of the chip via a dedicated IOCTL. + This driver is required for proper handling of temporary carrier + loss, so if you have a 25Mbps NICStAR based ATM card you must say Y. Madge Ambassador (Collage PCI 155 Server) CONFIG_ATM_AMBASSADOR --- 2.3.28.orig/drivers/atm/Config.in Thu Oct 7 18:17:09 1999 +++ 2.3.28.work/drivers/atm/Config.in Fri Nov 19 17:41:49 1999 @@ -31,9 +31,10 @@ # if [ "$CONFIG_ATM_TNETA1570" = "y" ]; then # bool ' Enable extended debugging' CONFIG_ATM_TNETA1570_DEBUG n # fi - tristate 'IDT 77201 (NICStAR)' CONFIG_ATM_NICSTAR + tristate 'IDT 77201 (NICStAR) (ForeRunnerLE)' CONFIG_ATM_NICSTAR if [ "$CONFIG_ATM_NICSTAR" != "n" ]; then - bool ' Use suni PHY driver' CONFIG_ATM_NICSTAR_USE_SUNI + bool ' Use suni PHY driver (155Mbps)' CONFIG_ATM_NICSTAR_USE_SUNI + bool ' Use IDT77015 PHY driver (25Mbps)' CONFIG_ATM_NICSTAR_USE_IDT77105 fi tristate 'Madge Ambassador (Collage PCI 155 Server)' CONFIG_ATM_AMBASSADOR if [ "$CONFIG_ATM_AMBASSADOR" != "n" ]; then --- 2.3.28.orig/drivers/atm/Makefile Wed Sep 8 19:14:31 1999 +++ 2.3.28.work/drivers/atm/Makefile Fri Nov 19 17:50:22 1999 @@ -43,12 +43,18 @@ ifeq ($(CONFIG_ATM_NICSTAR_USE_SUNI),y) NEED_SUNI_LX = suni.o endif + ifeq ($(CONFIG_ATM_NICSTAR_USE_IDT77105),y) + NEED_IDT77105_LX = idt77105.o + endif else ifeq ($(CONFIG_ATM_NICSTAR),m) M_OBJS += nicstar.o ifeq ($(CONFIG_ATM_NICSTAR_USE_SUNI),y) NEED_SUNI_MX = suni.o endif + ifeq ($(CONFIG_ATM_NICSTAR_USE_IDT77105),y) + NEED_SUNI_MX = idt77105.o + endif endif endif @@ -72,6 +78,12 @@ MX_OBJS += $(NEED_SUNI_MX) else LX_OBJS += $(NEED_SUNI_LX) +endif + +ifeq ($(NEED_IDT77105_LX),) + MX_OBJS += $(NEED_IDT77105_MX) +else + LX_OBJS += $(NEED_IDT77105_LX) endif ifeq ($(CONFIG_ATM_TCP),y) --- 2.3.28.orig/drivers/atm/idt77105.c Thu Jan 1 01:00:00 1970 +++ 2.3.28.work/drivers/atm/idt77105.c Fri Nov 19 18:13:14 1999 @@ -0,0 +1,385 @@ +/* drivers/atm/idt77105.c - IDT77105 (PHY) driver */ + +/* Written 1999 by Greg Banks, NEC Australia . Based on suni.c */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "idt77105.h" + +#undef GENERAL_DEBUG + +#ifdef GENERAL_DEBUG +#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args) +#else +#define DPRINTK(format,args...) +#endif + + +struct idt77105_priv { + struct idt77105_stats stats; /* link diagnostics */ + struct atm_dev *dev; /* device back-pointer */ + struct idt77105_priv *next; + int loop_mode; + unsigned char old_mcr; /* storage of MCR reg while signal lost */ +}; + + +#define PRIV(dev) ((struct idt77105_priv *) dev->phy_data) + +#define PUT(val,reg) dev->ops->phy_put(dev,val,IDT77105_##reg) +#define GET(reg) dev->ops->phy_get(dev,IDT77105_##reg) + +static void idt77105_stats_timer_func(unsigned long); +static void idt77105_restart_timer_func(unsigned long); + + +static struct timer_list stats_timer = { NULL, NULL, 0L, 0L, + &idt77105_stats_timer_func }; +static struct timer_list restart_timer = { NULL, NULL, 0L, 0L, + &idt77105_restart_timer_func }; +static int start_timer = 1; +static struct idt77105_priv *idt77105_all = NULL; + +/* + * Retrieve the value of one of the IDT77105's counters. + * `counter' is one of the IDT77105_CTRSEL_* constants. + */ +static u16 get_counter(struct atm_dev *dev, int counter) +{ + u16 val; + + /* write the counter bit into PHY register 6 */ + PUT(counter, CTRSEL); + /* read the low 8 bits from register 4 */ + val = GET(CTRLO); + /* read the high 8 bits from register 5 */ + val |= GET(CTRHI)<<8; + + return val; +} + +/* + * Timer function called every second to gather statistics + * from the 77105. This is done because the h/w registers + * will overflow if not read at least once per second. The + * kernel's stats are much higher precision. Also, having + * a separate copy of the stats allows implementation of + * an ioctl which gathers the stats *without* zero'ing them. + */ +static void idt77105_stats_timer_func(unsigned long dummy) +{ + struct idt77105_priv *walk; + struct atm_dev *dev; + struct idt77105_stats *stats; + + DPRINTK("IDT77105 gathering statistics\n"); + for (walk = idt77105_all; walk; walk = walk->next) { + dev = walk->dev; + + stats = &walk->stats; + stats->symbol_errors += get_counter(dev, IDT77105_CTRSEL_SEC); + stats->tx_cells += get_counter(dev, IDT77105_CTRSEL_TCC); + stats->rx_cells += get_counter(dev, IDT77105_CTRSEL_RCC); + stats->rx_hec_errors += get_counter(dev, IDT77105_CTRSEL_RHEC); + } + if (!start_timer) mod_timer(&stats_timer,jiffies+IDT77105_STATS_TIMER_PERIOD); +} + + +/* + * A separate timer func which handles restarting PHY chips which + * have had the cable re-inserted after being pulled out. This is + * done by polling the Good Signal Bit in the Interrupt Status + * register every 5 seconds. The other technique (checking Good + * Signal Bit in the interrupt handler) cannot be used because PHY + * interrupts need to be disabled when the cable is pulled out + * to avoid lots of spurious cell error interrupts. + */ +static void idt77105_restart_timer_func(unsigned long dummy) +{ + struct idt77105_priv *walk; + struct atm_dev *dev; + unsigned char istat; + + DPRINTK("IDT77105 checking for cable re-insertion\n"); + for (walk = idt77105_all; walk; walk = walk->next) { + dev = walk->dev; + + if (dev->signal != ATM_PHY_SIG_LOST) + continue; + + istat = GET(ISTAT); /* side effect: clears all interrupt status bits */ + if (istat & IDT77105_ISTAT_GOODSIG) { + /* Found signal again */ + dev->signal = ATM_PHY_SIG_FOUND; + printk(KERN_NOTICE "%s(itf %d): signal detected again\n", + dev->type,dev->number); + /* flush the receive FIFO */ + PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG); + /* re-enable interrupts */ + PUT( walk->old_mcr ,MCR); + } + } + if (!start_timer) mod_timer(&restart_timer,jiffies+IDT77105_RESTART_TIMER_PERIOD); +} + + +static int fetch_stats(struct atm_dev *dev,struct idt77105_stats *arg,int zero) +{ + unsigned long flags; + int error; + + error = 0; + save_flags(flags); + cli(); + if (arg) + error = copy_to_user(arg,&PRIV(dev)->stats, + sizeof(struct idt77105_stats)); + if (zero && !error) + memset(&PRIV(dev)->stats,0,sizeof(struct idt77105_stats)); + restore_flags(flags); + return error ? -EFAULT : sizeof(struct idt77105_stats); +} + + + +static int idt77105_ioctl(struct atm_dev *dev,unsigned int cmd,void *arg) +{ + printk(KERN_NOTICE "%s(%d) idt77105_ioctl() called\n",dev->type,dev->number); + switch (cmd) { + case IDT77105_GETSTATZ: + case IDT77105_GETSTAT: + return fetch_stats(dev,(struct idt77105_stats *) arg, + cmd == IDT77105_GETSTATZ); + case IDT77105_SETLOOP: + if (!capable(CAP_NET_ADMIN)) return -EPERM; + if ((int) arg < 0 || (int) arg > IDT77105_LM_LOOP) + return -EINVAL; + PUT((GET(DIAG) & ~IDT77105_DIAG_LCMASK) | + ((int) arg == IDT77105_LM_NONE ? IDT77105_DIAG_LC_NORMAL : 0) | + ((int) arg == IDT77105_LM_DIAG ? IDT77105_DIAG_LC_PHY_LOOPBACK : 0) | + ((int) arg == IDT77105_LM_LOOP ? IDT77105_DIAG_LC_LINE_LOOPBACK : 0), + DIAG); + printk(KERN_NOTICE "%s(%d) Loopback mode is: %s\n", + dev->type, dev->number, + ((int) arg == IDT77105_LM_NONE ? "NONE" : + ((int) arg == IDT77105_LM_DIAG ? "DIAG (local)" : + ((int) arg == IDT77105_LM_LOOP ? "LOOP (remote)" : + "unknown"))) + ); + PRIV(dev)->loop_mode = (int) arg; + return 0; + case IDT77105_GETLOOP: + return put_user(PRIV(dev)->loop_mode,(int *) arg) ? + -EFAULT : sizeof(int); + default: + return -EINVAL; + } +} + + + +static void idt77105_int(struct atm_dev *dev) +{ + unsigned char istat; + + istat = GET(ISTAT); /* side effect: clears all interrupt status bits */ + + DPRINTK("IDT77105 generated an interrupt, istat=%02x\n", (unsigned)istat); + + if (istat & IDT77105_ISTAT_RSCC) { + /* Rx Signal Condition Change - line went up or down */ + if (istat & IDT77105_ISTAT_GOODSIG) { /* signal detected again */ + /* This should not happen (restart timer does it) but JIC */ + dev->signal = ATM_PHY_SIG_FOUND; + } else { /* signal lost */ + /* + * Disable interrupts and stop all transmission and + * reception - the restart timer will restore these. + */ + PRIV(dev)->old_mcr = GET(MCR); + PUT( + (PRIV(dev)->old_mcr| + IDT77105_MCR_DREC| + IDT77105_MCR_DRIC| + IDT77105_MCR_HALTTX + ) & ~IDT77105_MCR_EIP, MCR); + dev->signal = ATM_PHY_SIG_LOST; + printk(KERN_NOTICE "%s(itf %d): signal lost\n", + dev->type,dev->number); + } + } + + if (istat & IDT77105_ISTAT_RFO) { + /* Rx FIFO Overrun -- perform a FIFO flush */ + PUT( GET(DIAG) | IDT77105_DIAG_RFLUSH, DIAG); + printk(KERN_NOTICE "%s(itf %d): receive FIFO overrun\n", + dev->type,dev->number); + } +#ifdef GENERAL_DEBUG + if (istat & (IDT77105_ISTAT_HECERR | IDT77105_ISTAT_SCR | + IDT77105_ISTAT_RSE)) { + /* normally don't care - just report in stats */ + printk(KERN_NOTICE "%s(itf %d): received cell with error\n", + dev->type,dev->number); + } +#endif +} + + +static int idt77105_start(struct atm_dev *dev) +{ + unsigned long flags; + + if (!(PRIV(dev) = kmalloc(sizeof(struct idt77105_priv),GFP_KERNEL))) + return -ENOMEM; + PRIV(dev)->dev = dev; + save_flags(flags); + cli(); + PRIV(dev)->next = idt77105_all; + idt77105_all = PRIV(dev); + restore_flags(flags); + memset(&PRIV(dev)->stats,0,sizeof(struct idt77105_stats)); + + /* initialise dev->signal from Good Signal Bit */ + dev->signal = GET(ISTAT) & IDT77105_ISTAT_GOODSIG ? ATM_PHY_SIG_FOUND : + ATM_PHY_SIG_LOST; + if (dev->signal == ATM_PHY_SIG_LOST) + printk(KERN_WARNING "%s(itf %d): no signal\n",dev->type, + dev->number); + + /* initialise loop mode from hardware */ + switch ( GET(DIAG) & IDT77105_DIAG_LCMASK ) { + case IDT77105_DIAG_LC_NORMAL: + PRIV(dev)->loop_mode = IDT77105_LM_NONE; + break; + case IDT77105_DIAG_LC_PHY_LOOPBACK: + PRIV(dev)->loop_mode = IDT77105_LM_DIAG; + break; + case IDT77105_DIAG_LC_LINE_LOOPBACK: + PRIV(dev)->loop_mode = IDT77105_LM_LOOP; + break; + } + + /* enable interrupts, e.g. on loss of signal */ + PRIV(dev)->old_mcr = GET(MCR); + if (dev->signal == ATM_PHY_SIG_FOUND) { + PRIV(dev)->old_mcr |= IDT77105_MCR_EIP; + PUT(PRIV(dev)->old_mcr, MCR); + } + + + idt77105_stats_timer_func(0); /* clear 77105 counters */ + (void) fetch_stats(dev,NULL,1); /* clear kernel counters */ + + cli(); + if (!start_timer) restore_flags(flags); + else { + start_timer = 0; + restore_flags(flags); + + init_timer(&stats_timer); + stats_timer.expires = jiffies+IDT77105_STATS_TIMER_PERIOD; + stats_timer.function = idt77105_stats_timer_func; + add_timer(&stats_timer); + + init_timer(&restart_timer); + restart_timer.expires = jiffies+IDT77105_RESTART_TIMER_PERIOD; + restart_timer.function = idt77105_restart_timer_func; + add_timer(&restart_timer); + } + return 0; +} + + +static const struct atmphy_ops idt77105_ops = { + idt77105_start, + idt77105_ioctl, + idt77105_int +}; + + +int __init idt77105_init(struct atm_dev *dev) +{ +#ifdef MODULE + MOD_INC_USE_COUNT; +#endif /* MODULE */ + + dev->phy = &idt77105_ops; + return 0; +} + + +/* + * TODO: this function should be called through phy_ops + * but that will not be possible for some time as there is + * currently a freeze on modifying that structure + * -- Greg Banks, 13 Sep 1999 + */ +int idt77105_stop(struct atm_dev *dev) +{ + struct idt77105_priv *walk, *prev; + + DPRINTK("%s(itf %d): stopping IDT77105\n",dev->type,dev->number); + + /* disable interrupts */ + PUT( GET(MCR) & ~IDT77105_MCR_EIP, MCR ); + + /* detach private struct from atm_dev & free */ + for (prev = NULL, walk = idt77105_all ; + walk != NULL; + prev = walk, walk = walk->next) { + if (walk->dev == dev) { + if (prev != NULL) + prev->next = walk->next; + else + idt77105_all = walk->next; + dev->phy = NULL; + PRIV(dev) = NULL; + kfree(walk); + break; + } + } + +#ifdef MODULE + MOD_DEC_USE_COUNT; +#endif /* MODULE */ + return 0; +} + + + +EXPORT_SYMBOL(idt77105_init); +EXPORT_SYMBOL(idt77105_stop); + +#ifdef MODULE + +int init_module(void) +{ + return 0; +} + + +void cleanup_module(void) +{ + /* turn off timers */ + del_timer(&stats_timer); + del_timer(&restart_timer); +} + +#endif --- 2.3.28.orig/drivers/atm/idt77105.h Thu Jan 1 01:00:00 1970 +++ 2.3.28.work/drivers/atm/idt77105.h Fri Nov 19 18:13:14 1999 @@ -0,0 +1,92 @@ +/* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */ + +/* Written 1999 by Greg Banks, NEC Australia . Based on suni.h */ + + +#ifndef DRIVER_ATM_IDT77105_H +#define DRIVER_ATM_IDT77105_H + +#include +#include + + +/* IDT77105 registers */ + +#define IDT77105_MCR 0x0 /* Master Control Register */ +#define IDT77105_ISTAT 0x1 /* Interrupt Status */ +#define IDT77105_DIAG 0x2 /* Diagnostic Control */ +#define IDT77105_LEDHEC 0x3 /* LED Driver & HEC Status/Control */ +#define IDT77105_CTRLO 0x4 /* Low Byte Counter Register */ +#define IDT77105_CTRHI 0x5 /* High Byte Counter Register */ +#define IDT77105_CTRSEL 0x6 /* Counter Register Read Select */ + +/* IDT77105 register values */ + +/* MCR */ +#define IDT77105_MCR_UPLO 0x80 /* R/W, User Prog'le Output Latch */ +#define IDT77105_MCR_DREC 0x40 /* R/W, Discard Receive Error Cells */ +#define IDT77105_MCR_ECEIO 0x20 /* R/W, Enable Cell Error Interrupts + * Only */ +#define IDT77105_MCR_TDPC 0x10 /* R/W, Transmit Data Parity Check */ +#define IDT77105_MCR_DRIC 0x08 /* R/W, Discard Received Idle Cells */ +#define IDT77105_MCR_HALTTX 0x04 /* R/W, Halt Tx */ +#define IDT77105_MCR_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */ +#define IDT77105_MCR_EIP 0x01 /* R/W, Enable Interrupt Pin */ + +/* ISTAT */ +#define IDT77105_ISTAT_GOODSIG 0x40 /* R, Good Signal Bit */ +#define IDT77105_ISTAT_HECERR 0x20 /* sticky, HEC Error*/ +#define IDT77105_ISTAT_SCR 0x10 /* sticky, Short Cell Received */ +#define IDT77105_ISTAT_TPE 0x08 /* sticky, Transmit Parity Error */ +#define IDT77105_ISTAT_RSCC 0x04 /* sticky, Rx Signal Condition Change */ +#define IDT77105_ISTAT_RSE 0x02 /* sticky, Rx Symbol Error */ +#define IDT77105_ISTAT_RFO 0x01 /* sticky, Rx FIFO Overrun */ + +/* DIAG */ +#define IDT77105_DIAG_FTD 0x80 /* R/W, Force TxClav deassert */ +#define IDT77105_DIAG_ROS 0x40 /* R/W, RxClav operation select */ +#define IDT77105_DIAG_MPCS 0x20 /* R/W, Multi-PHY config'n select */ +#define IDT77105_DIAG_RFLUSH 0x10 /* R/W, clear receive FIFO */ +#define IDT77105_DIAG_ITPE 0x08 /* R/W, Insert Tx payload error */ +#define IDT77105_DIAG_ITHE 0x04 /* R/W, Insert Tx HEC error */ +#define IDT77105_DIAG_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */ +#define IDT77105_DIAG_LCMASK 0x03 /* R/W, Loopback Control */ + +#define IDT77105_DIAG_LC_NORMAL 0x00 /* Receive from network */ +#define IDT77105_DIAG_LC_PHY_LOOPBACK 0x02 +#define IDT77105_DIAG_LC_LINE_LOOPBACK 0x03 + +/* LEDHEC */ +#define IDT77105_LEDHEC_DRHC 0x40 /* R/W, Disable Rx HEC check */ +#define IDT77105_LEDHEC_DTHC 0x20 /* R/W, Disable Tx HEC calculation */ +#define IDT77105_LEDHEC_RPWMASK 0x18 /* R/W, RxRef pulse width select */ +#define IDT77105_LEDHEC_TFS 0x04 /* R, Tx FIFO Status (1=empty) */ +#define IDT77105_LEDHEC_TLS 0x02 /* R, Tx LED Status (1=lit) */ +#define IDT77105_LEDHEC_RLS 0x01 /* R, Rx LED Status (1=lit) */ + +#define IDT77105_LEDHEC_RPW_1 0x00 /* RxRef active for 1 RxClk cycle */ +#define IDT77105_LEDHEC_RPW_2 0x08 /* RxRef active for 2 RxClk cycle */ +#define IDT77105_LEDHEC_RPW_4 0x10 /* RxRef active for 4 RxClk cycle */ +#define IDT77105_LEDHEC_RPW_8 0x18 /* RxRef active for 8 RxClk cycle */ + +/* CTRSEL */ +#define IDT77105_CTRSEL_SEC 0x08 /* W, Symbol Error Counter */ +#define IDT77105_CTRSEL_TCC 0x04 /* W, Tx Cell Counter */ +#define IDT77105_CTRSEL_RCC 0x02 /* W, Rx Cell Counter */ +#define IDT77105_CTRSEL_RHEC 0x01 /* W, Rx HEC Error Counter */ + +#ifdef __KERNEL__ +int idt77105_init(struct atm_dev *dev) __init; +int idt77105_stop(struct atm_dev *dev); +#endif + +/* + * Tunable parameters + */ + +/* Time between samples of the hardware cell counters. Should be <= 1 sec */ +#define IDT77105_STATS_TIMER_PERIOD (HZ) +/* Time between checks to see if the signal has been found again */ +#define IDT77105_RESTART_TIMER_PERIOD (5 * HZ) + +#endif --- 2.3.28.orig/drivers/atm/nicstar.c Wed Sep 8 19:14:31 1999 +++ 2.3.28.work/drivers/atm/nicstar.c Fri Nov 19 18:01:17 1999 @@ -44,6 +44,9 @@ #ifdef CONFIG_ATM_NICSTAR_USE_SUNI #include "suni.h" #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ +#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 +#include "idt77105.h" +#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ /* Additional code ************************************************************/ @@ -99,8 +102,10 @@ #define NS_DELAY mdelay(1) -#define ALIGN_ADDRESS(addr, alignment) \ +#define ALIGN_BUS_ADDR(addr, alignment) \ ((((u32) (addr)) + (((u32) (alignment)) - 1)) & ~(((u32) (alignment)) - 1)) +#define ALIGN_ADDRESS(addr, alignment) \ + bus_to_virt(ALIGN_BUS_ADDR(virt_to_bus(addr), alignment)) #undef CEIL(d) @@ -286,6 +291,12 @@ card = cards[i]; +#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 + if (card->max_pcr == IDT_25_PCR) { + idt77105_stop(card->atmdev); + } +#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ + /* Stop everything */ writel(0x00000000, card->membase + CFG); @@ -457,6 +468,7 @@ cards[i] = card; card->index = i; + card->atmdev = NULL; card->pcidev = pcidev; card->membase = (u32) pcidev->resource[1].start; #ifdef __powerpc__ @@ -872,8 +884,8 @@ card->atmdev->ci_range.vpi_bits = card->vpibits; card->atmdev->ci_range.vci_bits = card->vcibits; card->atmdev->link_rate = card->max_pcr; - card->atmdev->phy = NULL; + #ifdef CONFIG_ATM_NICSTAR_USE_SUNI if (card->max_pcr == ATM_OC3_PCR) { suni_init(card->atmdev); @@ -883,6 +895,17 @@ #endif /* MODULE */ } #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ + +#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 + if (card->max_pcr == IDT_25_PCR) { + idt77105_init(card->atmdev); + /* Note that for the IDT77105 PHY we don't need the awful + * module count hack that the SUNI needs because we can + * stop the '105 when the nicstar module is cleaned up. + */ + } +#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ + if (card->atmdev->phy && card->atmdev->phy->start) card->atmdev->phy->start(card->atmdev); @@ -2679,7 +2702,10 @@ card->intcnt = 0; return retval; } +#if 0 /* Dump 25.6 Mbps PHY registers */ + /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it + here just in case it's needed for debugging. */ if (card->max_pcr == IDT_25_PCR && !left--) { u32 phy_regs[4]; @@ -2696,6 +2722,7 @@ return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n", phy_regs[0], phy_regs[1], phy_regs[2], phy_regs[3]); } +#endif /* 0 - Dump 25.6 Mbps PHY registers */ #if 0 /* Dump TST */ if (left-- < NS_TST_NUM_ENTRIES) --- 2.3.28.orig/drivers/atm/nicstar.h Mon Aug 23 17:56:31 1999 +++ 2.3.28.work/drivers/atm/nicstar.h Fri Nov 19 18:09:50 1999 @@ -455,41 +455,59 @@ /* NISCtAR operation registers ************************************************/ +/* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */ + enum ns_regs { - DR0 = 0x00, - DR1 = 0x04, - DR2 = 0x08, - DR3 = 0x0C, - CMD = 0x10, - CFG = 0x14, - STAT = 0x18, - RSQB = 0x1C, - RSQT = 0x20, - RSQH = 0x24, - CDC = 0x28, - VPEC = 0x2C, - ICC = 0x30, - RAWCT = 0x34, - TMR = 0x38, - TSTB = 0x3C, - TSQB = 0x40, - TSQT = 0x44, - TSQH = 0x48, - GP = 0x4C, - VPM = 0x50 + DR0 = 0x00, /* Data Register 0 R/W*/ + DR1 = 0x04, /* Data Register 1 W */ + DR2 = 0x08, /* Data Register 2 W */ + DR3 = 0x0C, /* Data Register 3 W */ + CMD = 0x10, /* Command W */ + CFG = 0x14, /* Configuration R/W */ + STAT = 0x18, /* Status R/W */ + RSQB = 0x1C, /* Receive Status Queue Base W */ + RSQT = 0x20, /* Receive Status Queue Tail R */ + RSQH = 0x24, /* Receive Status Queue Head W */ + CDC = 0x28, /* Cell Drop Counter R/clear */ + VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */ + ICC = 0x30, /* Invalid Cell Count R/clear */ + RAWCT = 0x34, /* Raw Cell Tail R */ + TMR = 0x38, /* Timer R */ + TSTB = 0x3C, /* Transmit Schedule Table Base R/W */ + TSQB = 0x40, /* Transmit Status Queue Base W */ + TSQT = 0x44, /* Transmit Status Queue Tail R */ + TSQH = 0x48, /* Transmit Status Queue Head W */ + GP = 0x4C, /* General Purpose R/W */ + VPM = 0x50 /* VPI/VCI Mask W */ }; /* NICStAR commands issued to the CMD register ********************************/ + +/* Top 4 bits are command opcode, lower 28 are parameters. */ + #define NS_CMD_NO_OPERATION 0x00000000 + /* params always 0 */ + #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000 + /* b19{1=open,0=close} b18-2{SRAM addr} */ + #define NS_CMD_WRITE_SRAM 0x40000000 + /* b18-2{SRAM addr} b1-0{burst size} */ + #define NS_CMD_READ_SRAM 0x50000000 + /* b18-2{SRAM addr} */ + #define NS_CMD_WRITE_FREEBUFQ 0x60000000 + /* b0{large buf indicator} */ + #define NS_CMD_READ_UTILITY 0x80000000 + /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ + #define NS_CMD_WRITE_UTILITY 0x90000000 + /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000) #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION @@ -497,28 +515,33 @@ /* NICStAR configuration bits *************************************************/ -#define NS_CFG_SWRST 0x80000000 -#define NS_CFG_RXPATH 0x20000000 -#define NS_CFG_SMBUFSIZE_MASK 0x18000000 -#define NS_CFG_LGBUFSIZE_MASK 0x06000000 -#define NS_CFG_EFBIE 0x01000000 -#define NS_CFG_RSQSIZE_MASK 0x00C00000 -#define NS_CFG_ICACCEPT 0x00200000 -#define NS_CFG_IGNOREGFC 0x00100000 -#define NS_CFG_VPIBITS_MASK 0x000C0000 -#define NS_CFG_RCTSIZE_MASK 0x00030000 -#define NS_CFG_VCERRACCEPT 0x00008000 -#define NS_CFG_RXINT_MASK 0x00007000 -#define NS_CFG_RAWIE 0x00000800 -#define NS_CFG_RSQAFIE 0x00000400 -#define NS_CFG_RXRM 0x00000200 -#define NS_CFG_TMRROIE 0x00000080 -#define NS_CFG_TXEN 0x00000020 -#define NS_CFG_TXIE 0x00000010 -#define NS_CFG_TXURIE 0x00000008 -#define NS_CFG_UMODE 0x00000004 -#define NS_CFG_TSQFIE 0x00000002 -#define NS_CFG_PHYIE 0x00000001 +#define NS_CFG_SWRST 0x80000000 /* Software Reset */ +#define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */ +#define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */ +#define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */ +#define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue + Interrupt Enable */ +#define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */ +#define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */ +#define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */ +#define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */ +#define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */ +#define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */ +#define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt + Handling */ +#define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */ +#define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full + Interrupt Enable */ +#define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */ +#define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt + Enable */ +#define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ +#define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt + Enable */ +#define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt + Enable */ +#define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */ +#define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full + Interrupt Enable */ +#define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */ #define NS_CFG_SMBUFSIZE_48 0x00000000 #define NS_CFG_SMBUFSIZE_96 0x08000000 @@ -552,22 +575,22 @@ /* NICStAR STATus bits ********************************************************/ -#define NS_STAT_SFBQC_MASK 0xFF000000 -#define NS_STAT_LFBQC_MASK 0x00FF0000 -#define NS_STAT_TSIF 0x00008000 -#define NS_STAT_TXICP 0x00004000 -#define NS_STAT_TSQF 0x00001000 -#define NS_STAT_TMROF 0x00000800 -#define NS_STAT_PHYI 0x00000400 -#define NS_STAT_CMDBZ 0x00000200 -#define NS_STAT_SFBQF 0x00000100 -#define NS_STAT_LFBQF 0x00000080 -#define NS_STAT_RSQF 0x00000040 -#define NS_STAT_EOPDU 0x00000020 -#define NS_STAT_RAWCF 0x00000010 -#define NS_STAT_SFBQE 0x00000008 -#define NS_STAT_LFBQE 0x00000004 -#define NS_STAT_RSQAF 0x00000002 +#define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */ +#define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */ +#define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */ +#define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */ +#define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */ +#define NS_STAT_TMROF 0x00000800 /* Timer Overflow */ +#define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */ +#define NS_STAT_CMDBZ 0x00000200 /* Command Busy */ +#define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */ +#define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */ +#define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */ +#define NS_STAT_EOPDU 0x00000020 /* End of PDU */ +#define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ +#define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */ +#define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */ +#define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */ #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23) #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15) --- 2.3.28.orig/include/linux/atm_idt77105.h Thu Jan 1 01:00:00 1970 +++ 2.3.28.work/include/linux/atm_idt77105.h Fri Nov 19 18:13:14 1999 @@ -0,0 +1,40 @@ +/* atm_idt77105.h - Driver-specific declarations of the IDT77105 driver (for + * use by driver-specific utilities) */ + +/* Written 1999 by Greg Banks . Copied from atm_suni.h. */ + + +#ifndef LINUX_ATM_IDT77105_H +#define LINUX_ATM_IDT77105_H + +#include +#include + +/* + * Structure for IDT77105_GETSTAT and IDT77105_GETSTATZ ioctls. + * Pointed to by `arg' in atmif_sioc. + */ +struct idt77105_stats { + __u32 symbol_errors; /* wire symbol errors */ + __u32 tx_cells; /* cells transmitted */ + __u32 rx_cells; /* cells received */ + __u32 rx_hec_errors; /* Header Error Check errors on receive */ +}; + +#define IDT77105_GETLOOP _IOW('a',ATMIOC_PHYPRV,struct atmif_sioc) /* get loopback mode */ +#define IDT77105_SETLOOP _IOW('a',ATMIOC_PHYPRV+1,struct atmif_sioc) /* set loopback mode */ +#define IDT77105_GETSTAT _IOW('a',ATMIOC_PHYPRV+2,struct atmif_sioc) /* get stats */ +#define IDT77105_GETSTATZ _IOW('a',ATMIOC_PHYPRV+3,struct atmif_sioc) /* get stats and zero */ + + +/* + * TODO: what we need is a global loopback mode get/set ioctl for + * all devices, not these device-specific hacks -- Greg Banks + */ +#define IDT77105_LM_NONE 0 /* no loopback */ +#define IDT77105_LM_DIAG 1 /* diagnostic (i.e. loop TX to RX) + * (a.k.a. local loopback) */ +#define IDT77105_LM_LOOP 2 /* line (i.e. loop RX to TX) + * (a.k.a. remote loopback) */ + +#endif